According to a post to Chinese social media service Weibo, penned by Yungang Bao of the Institute of Computing Technology at the Chinese Academy of Sciences, the idea is to use the permissively licensed RISC-V ISA to create a high-performance chip, with the Scala source code .

Bao is a leader of the project, and has described the team's ambition to create a company that does for RISC-V what Red Hat did for Linux. The Xiangshan project has previously aspired to six-monthly releases, though it appears its latest design to be taped out was a second-gen chip named Nanhu that emerged in late 2023. That silicon ran at 2GHz and was built on a 14nm process node.

The project has since worked on a third-gen design, named Kunminghu, and published the image depicting an overview of its non-trivial micro-architecture.

Bao admits the project hasn’t progressed as quickly as hoped because developing high-end chips is hard.  The Xiangshan project spent 2024 “continuously optimising the area and power consumption of the third-generation Xiangshan (Kunming Lake architecture), and finally achieved a gap of less than eight per cent compared with N2.”