The introduction of 3D NAND flash - this year Micron is starting production of 96-layer devices - has circumvented the end of planar scaling, but 3D NAND has its scaling challenges including the same issues with high aspect-ration etches.

In addition, the challenges of maintaining nanometer-level uniformity in chips now scaling up to one terabit (125GB) are greater.

In a talk at this year's VLSI Symposia, Micron's Scott DeBoer said chipmakers need to find new ways to advance technology even as traditional scaling slows - including several more generations of DRAM over the next decade without the need for EUV lithography. Micron is using several techniques to mitigate these issues.

Last year, it began stacking two high-yielding 32-layer chips on top of one another to create a 64-layer device, which "really took te pressure off of the equipment suppliers for the most difficult part of 3D NAND, which is the etch through the layers". The latest third-generation 3D NAND is its second to use array stacking, combining two 48-layer chips, and the third to make use of CMOS Under the Array, and created the world's smallest 512Gb die.

DeBoar said that memory was at the beginning of a new era that of the "data economy" though the rest of the world generally calls it the AI era.

AI was a "game-changer" because these workloads use six times as much DRAM and twice the solid-state storage of a standard server in a cloud data centre. By last year, memory and storage had grown to a $128 billion market, and the world generated 22,000 billion gigabytes of data, according to Micron's estimates, he said.