Next generation 45 nanometre K10.5 codenamed Shanghai will remain at 512KB L2 per core but overall the CPU will have 6MB of Level 3 cache.

Intel's 45 nanometre Quad parts have 12 MB of L2 cache which means 3MB per core or six for each of two stitched processors.

Shanghai should have improved IPC and of course Hypertransport 3. it remains to be seen how will Barcelona K10 with its L2 + L3 cache go against 12 MB of L2 cache of Yorkfield 45 nanometre CPUs.


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AMD goes DDR 3 in late 2008