At the recent nanotech 2009 expo (INEC), partners Toshiba and SanDisk revealed a 300mm wafer with 32nm, 32-gigabit (4GB) NAND flash memory chips. Toshiba announced that is has already begun shipping samples out to its partners, with volume production of 32nm memory expected this September.

The NAND flash memory chips are based on 3-bit-per-cell architecture, which allows Toshiba to advance its cutting edge reputation by cramming more transistors into the world’s smallest die size. The company has said there are not any significant changes when compared to its current 2-bit-per-cell, 43nm wafers, which used a similar floating gate structure to manage the flow of power.

However, the 3-bit-per-cell generation devices use an optimized circuit design to deal with an extremely small write margin that comes as a result of dividing the threshold voltage in eight. For now, the company can deliver 32Gb (4GB) chips, but is planning to also sample 64Gb (8GB) products in July. This puts mass production of 32nm NAND products two months ahead of schedule. As the year progresses, 8GB 32nm chips are expected to start shipping out in Q4.

Toshiba also commented that it will begin production of memory in the 20-30 nanometer range around late 2010 or early 2011. Currently, its engineers are researching the possibility of maintaining a floating gate structure at smaller fabrications, or if they will need to shift to a new nitride trap to achieve the same effect. It has been speculated that floating gate transistors have reached their shrinkable limit with the ~30nm fabrications due to inter-cell interference. Yet only precious time and valuable research will determine the decision for the next leap in memory technology of such small magnitude.