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AMD talks up High Bandwidth Memory

by on20 May 2015


Thanks for the Memory

AMD's next-generation Radeon 300-series graphics cards are supposed to feature a High Bandwidth Memory (HBM) interface which there has been very little written about.

AMD, while not talking about the Radeon 300s has told Hot Hardware  a bit about the HBM which could also end up on future APUs.

High Bandwidth Memory fixes limitations of current GDDR5 memory. Large number of GDDR5 chips are necessary to offer sufficient capacity and bandwidth and they take up a lot of the PCB space. Routing the traces required for a wide memory interface on a high-end graphics card significantly increases the design complexity.

Shrinking and integrating functions onto the same piece of silicon can fix some of the problems but on-chip integration for DRAM is not size or cost effective.

AMD partnered up with a number of companies to help define a new specification and design new type of memory chip with low power consumption and an ultra-wide bus width. Hynix developed the HBM standard and memory, which was eventually adopted by JEDEC (document number JESD235) in October 2013. AMD also worked to develop a key component of the technology, called the interposer, along with ASE, Amkor, and UMC. The interposer allows DRAM to be brought into close proximity with the GPU and simplifies communication and clocking, even at very wide bus widths.

The vertically stacked HBM DRAM chips and "through-silicon vias" (TSVs) and "?bumps" are used to connect one DRAM chip to the next. This then connects to a logic die and then the interposer. TSVs and ?bumps are also used to connect the SoC/GPU to the interposer and the entire assembly is connected onto the same package substrate.
This creates a single package on which the GPU/SoC and High Bandwidth Memory both reside.

AMD said HBM is not only smaller than typical GDDR5 memory, but because it's vertically stacked, that same 1GB requires only about 35mm2. According to AMD, 9900mm2 of PCB footprint are required for an AMD Radeon R9 290X GPU and its associated memory, whereas <4900mm2 is required for an upcoming HBM-based ASIC.

Bus width on a HBM chip is 1024-bits wide, versus 32-bits on a GDDR5 chip which means that it can be clocked much lower. Wider memory bus and vertical stacking results in much more bandwidth—more than 100GB/s on HBM versus 28GB/s with GDDR5. HBM needs less juice .

In short HBM offers much more bandwidth than traditional GDDR5 at roughly half the power.

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